Introducing FeS2
We would like to announce the first public release of the FeS2 simulator.
FeS2 is a timing-first, multiprocessor, x86 simulator, implemented as a module for
Virtutech Simics.
Announcements
- (12/02/2010) Very nice FeS2 and Simics tutorials posted by Simha Sethumadhavan and his students
- (03/13/2009) 64-bit version of FeS2 released (svn r95)
- (10/01/2008) Multiprocessor version of FeS2 released (svn r50)
- (06/02/2008) Initial release of the FeS2 uniprocessor model (svn r30)
- (03/02/2008) Poster presented at ASPLOS 2008
FeS2 Features
- Open sourced under GPLv2
- Accurate execution-driven timing-model that includes a cache hierarchy, branch predictors
and a superscalar out-of-order core.
- Simulates the x86 ISA
- Enables research to use tools
that only exist on x86 or are much more mature on x86
(e.g. Pin, Apache Harmony). It also enables the evaluation of applications that are only
available as x86 binaries (e.g. Microsoft Word, Adobe Photoshop).
- Full-system simulation (i.e. simulates both user code and the operating
system)
- Necessary to correctly evaluate multi-threaded
applications. Multi-threaded applications are both affected by
operating-system thread-scheduling and communicate via operating-system
mechanisms such as signals.
- Multiprocessor memory model
- Relevant to many areas of research, FeS2 provides a detailed and flexible memory
system timing model. The memory model is provided by Ruby (leveraged from a pre-release version of
GEMS).
- Timing-first simulation methodology
- The known-good functional model
provided by Simics can run any x86 application and
operating system thereby enabling their evaluation with the mostly-correct
FeS2 timing model (which was easier to
implement).
- Micro-operation based core model
- Decodes x86 instructions into RISC like micro-operations (uops) as is
done in high-performance x86 implementations. The decoding of x86 instructions
into uops and the functional implementation of the uops is implemented using
code leveraged from PTLsim.
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